1. Field of the Invention
Embodiments of the invention relate to image sensors, and particularly to CMOS image sensors that perform simultaneous image sampling for all rows of pixels in the imaging array.
2. Related Technology
A simplified architecture of a CMOS image sensor is shown in FIG. 1. The image sensor is comprised of a two dimensional array of pixel circuits 110 that sample portions of an image. A row driver circuit 112 supplies control signals in common to the pixel circuits 110 in each row of the array. Pixel circuits 110 in each column provide pixel values in the form of analog voltages to column amplifiers 114, which drive the inputs of column AD converters 116 operating under the control of an ADC controller 118. Digital pixel values are supplied from the AD converters 116 to a RAM 120 having parallel inputs for each column. Pixel values are supplied to the RAM 120 on a row-by-row basis. In alternative embodiments, separate RAMs with associated ADCs and column amplifiers may be provided above and below the pixel array, with each RAM receiving data from odd or even columns of the pixel array.
Various methods of image sampling and readout control may be implemented. In one implementation referred to as a “rolling shutter,” the sampling period for each row of pixels begins after the signals from its previous sampling period have been read out to the column amplifiers 114. Rolling shutter image sensors based on a four-transistor pixel structure and pinned photodiode exhibit low noise and high sensitivity, and are the dominant image sensor for a majority of consumer applications. However the rolling shutter method is undesirable for use in high-speed moving image applications since the sampling period of each row is offset in time from that of the next row, thus introducing row to row motion artifacts into the resulting image.
An alternative to the rolling shutter method is a parallel sampling method in which all pixels sample the image during the same time period and then output the sampled signals row by row. FIG. 2 shows an example of a pixel circuit in a conventional CMOS image sensor that performs parallel sampling. During exposure, a photodiode 122 produces photocurrent which is integrated to produce a charge at the photodiode node 124. The storage capacity of the photodiode node 124 is shown in broken lines as an equivalent capacitance 126. When exposure is completed, the accumulated charge is transferred from the photodiode node 124 to a memory node 128 through a transfer gate 130. The transfer gate 130 is implemented as a MOSFET, and the capacitance 132 of the MOSFET source/drain serves as a memory element for storing the charge. After transfer of the accumulated charge, the photodiode node 124 is reset through application of a reset voltage Vrst through a photodiode reset gate 134.
Operation of a row select gate 136 causes a signal to be read out onto a column line 138 through a source follower 140 that is powered by a driving voltage Vdd and that has its gate connected to the memory node 128. Signals from the column line are supplied to a column amplifier 142. The column amplifier 142 is implemented as a differential amplifier that outputs the difference of an image signal voltage read from the column line 138 and a reset signal voltage subsequently read from the column line 138. A charge stored in the memory node 128 is used to generate each of these voltages. The image signal voltage corresponds to the charge transferred from the photodiode node 124 to the memory node 128. The reset signal voltage corresponds to a charge stored in the memory node 128 after application of the reset voltage Vrst to the memory node 128 through a memory reset gate 144. At the column amplifier 142, the image signal voltage is stored in a signal storage element 146 controlled by a gate 148, and a subsequent reset signal voltage is stored in a reset storage element 150 controlled by a gate 152. The storage elements 146 and 150 may be implemented as capacitors.
FIG. 3 provides a timing diagram showing gate control signals provided by the row driver 12 of FIG. 1 to the pixel circuit of FIG. 2 and operations resulting from those control signals. The operations include global operations that cause image exposure at all pixels, and single row operations that cause all pixels of an individual row to be read out in parallel. For purposes of illustration, the timing diagram of FIG. 3 shows all global operations, followed by single row operations for the first row of pixels to be read out. However, as will be discussed below, the global operations may overlap the single row operations.
The global operations include a photodiode (PD) reset, during which the photodiode reset gates 134 of all pixels in the array are opened to reset the values stored in the photodiode nodes 124 through application of the reset voltage Vrst. After the photodiode reset operation is completed, image exposure occurs, during which all pixel circuits are exposed to light and generate photocurrent that is integrated to create charges representing pixel values of an image. A transfer operation then occurs, during which the transfer gates 130 of all pixel circuits are opened to transfer the charges accumulated in the photodiode nodes 124 to the corresponding memory nodes 128.
The single row operations for a given row begin with an image signal readout operation, during which the row select gates 136 of all pixel circuits in the row are opened to read image signals corresponding to the charges stored in the pixel circuit memory nodes 128 onto the corresponding column lines 138. During the image signal readout operation a control signal SH_S causes image signal voltages on the column lines to be stored in image signal storage elements 146 at the inputs of the column amplifiers 142. After the image signal readout operation is complete, a memory reset operation is performed, during which the memory reset gates 144 are opened to apply the reset voltage Vrst to the memory nodes 128. After the memory reset operation is complete, a reset signal readout operation occurs, during which the row select gates 136 are opened to read reset signal voltages corresponding to the reset charges stored in the memory nodes 128 onto the corresponding column lines. During this operation a control signal SH_R causes the reset signal voltages on the column lines 138 to be stored in the reset signal storage elements 150 at the inputs of the column amplifiers 142. Upon completion of this operation, each column amplifier 142 of the array outputs a voltage representing the difference between the signal voltage and the reset voltage of a respective pixel in the row. These voltages are supplied as inputs to AD converters to generate respective digital pixel values. The illustrated series of single row operations is repeated for each successive row of the pixel array to read out all pixels of the pixel array.
From the timing of FIG. 3 it is seen that the transfer gate remains closed during all single row operations, thus isolating the photodiode node from the single row operations. A new exposure period may therefore begin at any time after the transfer gate is closed, allowing an image to be exposed while pixel values of the preceding image are being read out. The breaks in the control signals of FIG. 3 during the global operations period are provided to illustrate that single row operations may occur during the exposure period between the photodiode reset operation and the transfer operation.
Certain disadvantages are experienced with the pixel circuit of the type shown in FIG. 2. The feedthrough of the photodiode reset gate 134 is a function of the photodiode node 124 equivalent capacitance, and the feedthrough of the memory reset gate 144 is a function of the memory node 128 capacitance. The gate feedthrough is manifested as a difference between the reset voltage Vrst and the voltage at the photodiode node 124 or memory node 128 after application of the reset voltage Vrst through the respective gate. The differences in the feedthroughs of the photodiode reset gate 134 and the memory reset gate 144 yield different voltages after reset at the photodiode node 124 and memory node 128 as a result of charge injected into those node upon closing the respective gates. The transfer gate 130 feedthrough also affects the voltage transferred from the photodiode node 124 to the memory node 128. These feedthrough values are a function of a number of parameters including device geometries, threshold voltages and others, and are different at each pixel circuit. Consequently, while the effects of feedthrough at each pixel are essentially constant from cycle to cycle, the signal produced by each pixel circuit includes a feedthrough component that is different at each pixel. This produces “fixed pattern noise” or dark signal nonuniformity in the sampled image. The magnitude of the dark signal nonuniformity in an image sensor having pixel circuits of the type shown in FIG. 2 may be in the range of 30 mV peak-to-peak.